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HV632
HV632
Initial Release
32-Channel 256 Gray-Shade High Voltage Driver
Features
HVCMOS(R) technology 5V CMOS inputs Up to 80V output voltage PWM gray shade conversion Capable of 256 levels of gray shading 10MHz shift and count clock frequency 20MHz data throughput rate 8 bit data bus 32 outputs per device BLANK function Output polarity control
General Description
The HV632 is a 32-channel gray-shade column driver IC designed for driving electrofluorescent displays. Using Supertex's unique HVCMOS(R) technology, it is capable of 256 levels of gray shading by PWM conversion. Input data, in groups of eight, is latched into a set of data latches on both edges of the shift clock. The data shifted in the first data latch corresponds to HVOUT1, the second data latch corresponds to HVOUT2, and so on. These data are compared to the contents of the master binary counter which counts on both edges of the count clock. Each time the master counter begins to decrement from 1111 1111, the data in the data latches are compared with the contents of the counter; if they match, the corresponding outputs will go high. The master counter counts down to 0000 0001 and then starts to count up again. The outputs that are at high will stay at high until the contents of the counter match the data in the data latches again. Therefore, the higher the binary data in the data latches, the longer the outputs will stay at high. Thus, different high voltage pulse widths are produced. When the counter reaches its 1111 1111 count while counting up, the device is ready for the next operation cycle. A data value of 0000 0000 produces no pulse; the output stays low. The BLANK input signal will reset the master counter to all ones (1111 1111) and set all high voltage outputs to low, or will set all high voltage outputs to high state, when the POL is low. The POL input signal, forced low, will invert the polarity of the output pulse. If left unconnected, POL input will be pulled high to VDD by an onchip resistor.
Applications
Field Emission Displays (FED) Polymer Liquid Crystal Displays (PLCD) Vacuum Fluorescent Displays (VFD)
Typical Application
Low Voltage Power Supply DIN(1-8) SC CSI Micro Processor CC LC BL POL CSO Shift Register CSI for cascading the next HV632
07/08/03
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
High Voltage Power Supply High Voltage HVout1
Supertex HV632
Colunms (Cathodes)
Low Voltage
32 Latches Counter Comparators
Level Translators & Push-Pull Output Buffers HVout32
Display Panel (FED)
Scan Driver HV57908
1
HV632
Ordering Information
Package Option Device HV632 64-Lead 3-Sided Plastic Gullwing HV632PG Die HV632X
Absolute Maximum Ratings
Supply voltage, VDD Supply voltage, VPP Logic input levels Continuous total power dissipation Operating temperature range Storage temperature range -0.5V to +7.5V -0.5V to +90V -0.5 to VDD + 0.5V 1.2W -40C to +85C -65C to +150C
Notes: All voltages are referenced to GND. For operation above 25C ambient derate linearly to 85C at 20mW/C.
Electrical Characteristics
(Over recommended conditions of VDD = 5V, VPP = 80V, TA = 25C unless otherwise noted)
Low-Voltage DC Characteristics (Digital)
Symbol VDD IDD IDDQ IIH IIL IOH IOL Parameter Low-voltage digital supply voltage VDD supply current Quiescent VDD supply current High-level input current Low-level input current High-level output current Low-level ouptut current Min 4.5 Max 5.5 25 150 10 -10 Units V mA A A A mA mA Conditions fSC = 10MHz, fCC = 10MHz All VIN = GND, Count Clock = VDD VIN = VDD VIL = GND VOUT=0.9 VDD VOUT=0.1 VDD
-1.0 1.0
High-Voltage DC Characteristics
Symbol IPPQ IOUT(p) IOUT(n) IPP Parameter Quiescent VPP supply current P-channel output current N-channel output current VPP supply current Min -4.0 4.0 1.1 Max 100 Units A mA mA mA Conditions All HVOUT low or high HVOUT=75V HVOUT=5V CL=0pF, FCC=10Mhz
2
HV632
Electrical Characteristics
(Over recommended conditions of VDD = 5V, VPP = 80V, TA = 25C unless otherwise noted)
AC Characteristics
Symbol fSC fCC fDIN tCW tCSS tCSH tSCC tDSS tDSH tDW tLCW tCCW tCCC tLCD tCCD tBLW tBLD tCDD tCSOH tCSOL Parameter Shift clock frequency Count clock frequency Data In frequency Chip select pulse width Chip select to shift clock set-up time Chip select to shift clock hold time Shift clock cycle time Data to shift clock set-up time Data to shift clock hold time Data In pulse width Load count pulse width Count clock pulse width Count clock cycle time Load count to count clock delay Count clock to HVOUT turn-on/turn-off BLANK pulse width BLANK to HVOUT delay Count clock delay between count down and count up cycles CSO delay output for High CSO delay output for Low Min Max 10 10 20 Units MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions
80 5.0 15 100 10 40 50 75 50 100 100 300 700 500 150 40 40
CL = 15pF CL = 15pF
CL=15pF CL=15pF
Recommended Operating Conditions
Symbol VDD VPP VIL VIH TA Parameter Logic supply voltage Positive high-voltage supply Low-level input voltage High-level input voltage Operating temperature Min 4.5 12 0 VDD-1 -40 Max 5.5 80 1 VDD +85 Units V V V V C Conditions
Pin Definitions
Pin # 27-30 36-39 34 31 32 24 25 33 26 4-19 46-61 23,43 40 22,44 20-21 Name D1 - D8 Shift Clock Count Clock POL CSI CSO Load Count Blank HVOUT1 - HVOUT32 VPP VDD HVGND GND I/O I I I I I O I I O -- -- -- -- Function Inputs for binary-format parallel data (D8 is the most significant bit) Triggers data on both edges Input to the counter Output polarity control Chip select input to enable the device to accept data Chip select output to enable the next device Input to initiate the counting Input to reset the counter and HVOUT High-voltage outputs Positive high-voltage supply Low-voltage digital supply voltage High voltage ground Digital ground 3
HV632
Functional Block Diagram
8 Bit Data In > 8 POL* 8 VPP VPP
Data Latch 1
>
Comparator & Latch 1 8
Logic
L/T
HVOUT1
>
Data Latch 2
8
Comparator & Latch 2 8
Logic
L/T
HVOUT2
>
Data Latch 3
8
Comparator & Latch 3
Logic
L/T
HVOUT3
> Data Latch 32 8
8
Logic
L/T
* * *
HVOUT32 HVGND
Comparator & Latch 32 8
>
HVGND > Count Clock
>
Logic
8 Bit Counter
>
>
CSO
Shift Clock
CSI
>
Load Count
>
Blank
L/T = Level Translator
* Internal pull-up resistor
4
HV632
Input and Output Equivalent Circuits
VDD VDD VPP
Input
Data Out
HVOUT
GND Logic Inputs
GND Logic Data Output
HVGND High Voltage Output
Timing Diagrams
CSI Shift Clock
253 253 254 254 255 255
1
2
3
4
16
1
2
3
4
16
VALID DATA
VALID DATA
CSO
LC Count Clock
255 255
254 254
253 253
252 252
1 1
1 1
HVOUT
5
252 252
HV632
Timing Diagrams
t CSOH t CSOL
VIH CSO
LOADING LAST DEVICE NEXT LOADING CYCLE
VIL
t CW
VIH
50%
CSI
t CSS t CSH
50%
VIL
t SCC
VIH
SC1
SC2
SC16
SC1

Shift Clock Data 1-8
SCN
VIL VIH
50%
DATA SET 1
DATA SET 2
DATA SET 3
DATA SET 31
DATA SET 32
DATA SET 1
DATA SET 2
DATA SET 2N -1
DATA SET 2N
VIL
t DSS
t DSH
t DW t LCW
VIH
50% 50%
Load Count Count Clock
t LCD
50% 50%
t CCW
50%
t CCC
50%
VIL VIH
50%
VIL VPP
t CCD
90%
t CCD
90%
HVOUT
t BLW
10%
10%
HVGND VIH
50%
50%
t BLD
HVOUT
BLANK
90%
VIL VPP
HVGND
t CDD
Count Clock
255
VIH
50% 1 2 3
50% 254 3 2 1
VIL
6
HV632
Pin Configurations
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Function N/C N/C N/C HVOUT17 HVOUT18 HVOUT19 HVOUT20 HVOUT21 HVOUT22 HVOUT23 HVOUT24 HVOUT25 HVOUT26 HVOUT27 HVOUT28 HVOUT29 HVOUT30 HVOUT31 HVOUT32 GND GND HVGND VPP CSI CSO Blank D1 D2 D3 D4 Count Clock POL Pin 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Function Load Count Shift Clock N/C D5 D6 D7 D8 VDD NC NC VPP HVGND N/C HVOUT1 HVOUT 2 HVOUT 3 HVOUT 4 HVOUT 5 HVOUT 6 HVOUT 7 HVOUT 8 HVOUT 9 HVOUT10 HVOUT11 HVOUT12 HVOUT13 HVOUT14 HVOUT15 HVOUT16 N/C N/C N/C
Package Outline
1
Index
64
24 25 top view 40
41
3-sided Plastic 64-pin Gullwing Package
7
HV632
Package Outline
64-Lead 3-Sided Plastic Quad Flat Package (PG) ("Gullwing" Package)
D
0.884 0.004 (22.4536 0.1016)
0.015 0.003 (0.381 0.0762)
L1
E
0.705 0.004 (17.907 0.102)
0.015 0.003 (0.381 0.0762)
B
0.040 REF (1.016)
E1
0.547 0.004 (13.8938 0.1016)
e
0.0315 (0.800)
D1
0 - 10
0.782 0.004 (19.8628 0.1016) 0.106 0.010 (2.692 0.254)
A2
0 - 7
A
0.118 0.010 (2.9972 0.254)
L
0.031 0.005 (0.7874 0.127)
Note: Circle (e.g. B ) indicates JEDEC Reference.
Measurement Legend =
Dimensions in Inches (Dimensions in Millimeters)
07/08/03rev.2
(c)2003 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
8
1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 222-8888 * FAX: (408) 222-4895 www.supertex.com

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